Microprocessor MCQ (Multiple Choice Questions) - SchoolingAxis

Microprocessor MCQ (Multiple Choice Questions)

 1. The registers that store the keyboard and display modes and operations programmed by CPU are

a. I/O control and data buffers

b. Control and timing registers

c. Return buffers

d. Display address registers

Ans- b. Control and timing registers

2. In the application where all the interrupting devices are of equal priority, the mode used is

a. Automatic rotation

b. Automatic EOI mode

c. Specific rotation

d. EOI

Ans- a. Automatic rotation

3. When non-specific EOI command is issued to 8259A it will automatically

a. set the ISR

b. reset the ISR

c. set the INTR

d. reset the INTR

Ans- b. reset the ISR

4. Once the ICW1 is loaded, then the initialization procedure involves

a. edge sense circuit is reset

b. IMR is cleared

c. slave mode address is set to 7

d. all of the mentioned

Ans- d. all of the mentioned

5. When the PS(active low)/EN(active low) pin of 8259A used in buffered mode, then it can be used as a

input to designate chip is a. master or slave

b. buffer enable

c. buffer disable

d. none

Ans- b. buffer enable

6. In a cascaded mode, the number of vectored interrupts provided by 8259A is

a. 4

b. 8

c. 16

d. 64

Ans- d. 64

7. The interrupt control logic

a. manages interrupts

b. manages interrupt acknowledge signals

c. accepts interrupt acknowledge signal

d. all of the mentioned

Ans- d. all of the mentioned

8. The register that stores the bits required to mask the interrupt inputs is

a. In-service register

b. Priority resolver

c. Interrupt Mask register

d. None

Ans- c. Interrupt Mask register

9. The register that stores all the interrupt requests in it in order to serve them one by one on a priority basis is

a. Interrupt Request Register

b. In-Service Register

c. Priority resolver

d. Interrupt Mask Register

Ans- a. Interrupt Request Register

10. The number of hardware interrupts that the processor 8085 consists of is

a. 1

b. 3

c. 5

d. 7

Ans- c. 5

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