Operating System MCQ (Multiple Choice Questions) - SchoolingAxis

Operating System MCQ (Multiple Choice Questions)

 Que- When the memory allocated to a process is slightly larger than the process, then : 

a. internal fragmentation occurs 

b. external fragmentation occurs 

c. both internal and external fragmentation occurs 

d. neither internal nor external fragmentation occurs 


Answer- internal fragmentation occurs        


Que- Physical memory is broken into fixed-sized blocks called ________ 

a. frames 

b. pages 

c. backing store 

d. none of the mentioned 


Answer- frames        


Que- Logical memory is broken into blocks of the same size called _________ 

a. frames 

b. pages 

c. backing store 

d. none of the mentioned 


Answer- pages        


Que- Every address generated by the CPU is divided into two parts : 

a. frame bit & page number 

b. page number & page offset 

c. page offset & frame bit 

d. frame offset & page offset 


Answer- page number & page offset        


Que- The __________ is used as an index into the page table. 

a. frame bit 

b. page number 

c. page offset 

d. frame offset 


Answer- page number        


Que- The _____ table contains the base address of each page in physical memory. 

a. process 

b. memory 

c. page 

d. frame 


Answer- page        


Que- The size of a page is typically : 

a. varied 

b. power of 2 

c. power of 4 

d. none of the mentioned 


Answer- power of 2        


Que- If the size of logical address space is 2 to the power of m, and a page size is 2 to the power of n addressing units, then the high order _____ bits of a logical address designate the page number, and the ____ low order bits designate the page offset. 

a. m, n 

b. n, m 

c. m - n, m 

d. m - n, n 


Answer- m - n, n        


Que- With paging there is no ________ fragmentation. 

a. internal 

b. external 

c. either type of 

d. none of the mentioned 


Answer- external        


Que- The operating system maintains a ______ table that keeps track of how many frames have been allocated, how many are there, and how many are available. 

a. page 

b. mapping 

c. frame 

d. memory 


Answer- frame        


Que- Paging increases the ______ time. 

a. waiting 

b. execution 

c. context - switch 

d. all of the mentioned 


Answer- context - switch        


Que- Smaller page tables are implemented as a set of _______ 

a. queues 

b. stacks 

c. counters 

d. registers 


Answer- registers        


Que- The page table registers should be built with _______ 

a. very low speed logic 

b. very high speed logic 

c. a large memory space 

d. none of the mentioned 


Answer- very high speed logic        


Que- For larger page tables, they are kept in main memory and a __________ points to the page table. 

a. page table base register 

b. page table base pointer 

c. page table register pointer 

d. page table base 


Answer- page table base register        


Que- For every process there is a __________ 

a. page table 

b. copy of page table 

c. pointer to page table 

d. all of the mentioned 


Answer- page table        


Que- Time taken in memory access through PTBR is : 

a. extended by a factor of 3 

b. extended by a factor of 2 

c. slowed by a factor of 3 

d. slowed by a factor of 2 


Answer- slowed by a factor of 2        


Que- Each entry in a Translation lookaside buffer (TLB) consists of : 

a. key 

b. value 

c. bit value 

d. constant 


Answer- key        


Que- If a page number is not found in the TLB, then it is known as a : 

a. TLB miss 

b. Buffer miss 

c. TLB hit 

d. All of the mentioned 


Answer- TLB miss        


Que- An ______ uniquely identifies processes and is used to provide address space protection for that process. 

a. address space locator 

b. address space identifier 

c. address process identifier 

d. None of the mentioned 


Answer- address space identifier        


Que- The percentage of times a page number is found in the TLB is known as : 

a. miss ratio 

b. hit ratio 

c. miss percent 

d. None of the mentioned 


Answer- hit ratio        


Que- Memory protection in a paged environment is accomplished by : 

a. protection algorithm with each page 

b. restricted access rights to users 

c. restriction on page visibility 

d. protection bit with each page 


Answer- protection bit with each page        


Que- When the valid - invalid bit is set to valid, it means that the associated page : 

a. is in the TLB 

b. has data in it 

c. is in the process's logical address space 

d. is the system's physical address space 


Answer- is in the process's logical address space        


Que- Illegal addresses are trapped using the _____ bit. 

a. error 

b. protection 

c. valid - invalid 

d. access 


Answer- valid - invalid        


Que- When there is a large logical address space, the best way of paging would be : 

a. not to page 

b. a two level paging algorithm 

c. the page table itself 

d. all of the mentioned 


Answer- a two level paging algorithm        


Que- To obtain better memory utilization, dynamic loading is used. With dynamic loading, a routine is not loaded until it is called. For implementing dynamic loading, 

a. special support from hardware is required 

b. special support from operating system is essential 

c. special support from both hardware and operating system is essential 

d. user programs can implement dynamic loading without any special support from hardware or operating system 


Answer- user programs can implement dynamic loading without any special support from hardware or operating system        


Que- In paged memory systems, if the page size is increased, then the internal fragmentation generally : 

a. becomes less 

b. becomes more 

c. remains constant 

d. none of the mentioned 


Answer- becomes more        


Que- In segmentation, each address is specified by : 

a. a segment number & offset 

b. an offset & value 

c. a value & segment number 

d. a key & value 


Answer- a segment number & offset        


Que- In paging the user provides only ________ which is partitioned by the hardware into ________ and ______ 

a. one address, page number, offset 

b. one offset, page number, address 

c. page number, offset, address 

d. none of the mentioned 


Answer- one address, page number, offset        


Que- Each entry in a segment table has a : 

a. segment base 

b. segment peak 

c. segment value 

d. none of the mentioned 


Answer- segment base        


Que- The segment base contains the : 

a. starting logical address of the process 

b. starting physical address of the segment in memory 

c. segment length 

d. none of the mentioned 


Answer- starting physical address of the segment in memory        


Que- The segment limit contains the : 

a. starting logical address of the process 

b. starting physical address of the segment in memory 

c. segment length 

d. none of the mentioned 


Answer- segment length        


Que- The offset 'd' of the logical address must be : 

a. greater than segment limit 

b. between 0 and segment limit 

c. between 0 and the segment number 

d. greater than the segment number 


Answer- between 0 and segment limit        


Que- If the offset is legal : 

a. it is used as a physical memory address itself 

b. it is subtracted from the segment base to produce the physical memory address 

c. it is added to the segment base to produce the physical memory address 

d. none of the mentioned 


Answer- it is used as a physical memory address itself        


Que- When the entries in the segment tables of two different processes point to the same physical location : 

a. the segments are invalid 

b. the processes get blocked 

c. segments are shared 

d. all of the mentioned 


Answer- segments are shared        


Que- The protection bit is 0/1 based on : 

a. write only 

b. read only 

c. read - write 

d. none of the mentioned 


Answer- read - write        


Que- If there are 32 segments, each of size 1Kb, then the logical address should have : 

a. 13 bits 

b. 14 bits 

c. 15 bits 

d. 16 bits 


Answer- 13 bits        


Que- Consider a computer with 8 Mbytes of main memory and a 128K cache. The cache block size is 4 K. It uses a direct mapping scheme for cache management. How many different main memory blocks can map onto a given physical cache block ? 

a. 2048 

b. 256 

c. 64 

d. 8 


Answer- 64        


Que- A multilevel page table is preferred in comparison to a single level page table for translating virtual address to physical address because : 

a. it reduces the memory access time to read or write a memory location 

b. it helps to reduce the size of page table needed to implement the virtual address space of a process 

c. it is required by the translation lookaside buffer 

d. it helps to reduce the number of page faults in page replacement algorithms 


Answer- it helps to reduce the size of page table needed to implement the virtual address space of a process        


Que- If one or more devices use a common set of wires to communicate with the computer system, the connection is called ______ 

a. CPU 

b. Monitor 

c. Wirefull 

d. Bus 


Answer- Bus        


Que- A ____  a set of wires and a rigidly defined protocol that specifies a set of messages that can be sent on the wires. 

a. port 

b. node 

c. bus 

d. none of the mentioned 


Answer- bus        


Que- When device A has a cable that plugs into device B, and device B has a cable that plugs into device C and device C plugs into a port on the computer, this arrangement is called a _________ 

a. port 

b. daisy chain 

c. bus 

d. cable 


Answer- daisy chain        


Que- The _________ present a uniform device-access interface to the I/O subsystem, much as system calls provide a standard interface between the application and the operating system. 

a. Devices 

b. Buses 

c. Device drivers 

d. I/O systems 


Answer- Device drivers        


Que- A ________ is a collection of electronics that can operate a port, a bus, or a device. 

a. controller 

b. driver 

c. host 

d. bus 


Answer- controller        


Que- An I/O port typically consists of four registers status, control, ________ and ________ registers. 

a. system in, system out 

b. data in, data out 

c. flow in, flow out 

d. input, output 


Answer- data in, data out        


Que- The ______ register is read by the host to get input. 

a. flow in 

b. flow out 

c. data in 

d. data out 


Answer- data in        


Que- The ______ register is written by the host to send output. 

a. status 

b. control 

c. data in 

d. data out 


Answer- data out        


Que- The hardware mechanism that allows a device to notify the CPU is called _______ 

a. polling 

b. interrupt 

c. driver 

d. controlling 


Answer- interrupt        


Que- The CPU hardware has a wire called __________ that the CPU senses after executing every instruction. 

a. interrupt request line 

b. interrupt bus 

c. interrupt receive line 

d. interrupt sense line 


Answer- interrupt request line        


Que- The _________ determines the cause of the interrupt, performs the necessary processing and executes a return from the interrupt instruction to return the CPU to the execution state prior to the interrupt. 

a. interrupt request line 

b. device driver 

c. interrupt handler 

d. all of the mentioned 


Answer- interrupt handler        


Que- In general the two interrupt request lines are : 

a. maskable & non maskable interrupts 

b. blocked & non maskable interrupts 

c. maskable & blocked interrupts 

d. none of the mentioned 


Answer- maskable & non maskable interrupts        


Que- The _________ are reserved for events such as unrecoverable memory errors. 

a. non maskable interrupts 

b. blocked interrupts 

c. maskable interrupts 

d. none of the mentioned 


Answer- non maskable interrupts        


Que- The ________ can be turned off by the CPU before the execution of critical instruction sequences that must not be interrupted. 

a. nonmaskable interrupt 

b. blocked interrupt 

c. maskable interrupt 

d. none of the mentioned 


Answer- maskable interrupt        


Que- The __________ is used by device controllers to request service. 

a. nonmaskable interrupt 

b. blocked interrupt 

c. maskable interrupt 

d. none of the mentioned 


Answer- maskable interrupt        


Que- The interrupt vector contains : 

a. the interrupts 

b. the memory addresses of specialized interrupt handlers 

c. the identifiers of interrupts 

d. the device addresses 


Answer- the memory addresses of specialized interrupt handlers        


Que- Division by zero, accessing a protected or non existent memory address, or attempting to execute a privileged instruction from user mode are all categorized as ________ 

a. errors 

b. exceptions 

c. interrupt handlers 

d. all of the mentioned 


Answer- exceptions        


Que- For large data transfers, _________ is used. 

a. dma 

b. programmed I/O 

c. controller register 

d. none of the mentioned 


Answer- dma        


Que- A character stream device transfers : 

a. bytes one by one 

b. block of bytes as a unit 

c. with unpredictable response times 

d. none of the mentioned 


Answer- bytes one by one        


Que- A block device transfers : 

a. bytes one by one 

b. block of bytes as a unit 

c. with unpredictable response times 

d. none of the mentioned 


Answer- block of bytes as a unit        


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