# Counters in Digital Logic Design MCQs

Q1. A MOD-16 ripple counter is holding the count 1001(2). What will the count be after 31 clock pulses?.

A. 1000(2).

B. 1010(2).

C. 1011(2).

D. 1101(2).

Q2. The terminal count of a modulus-11 binary counter is ________..

A. 1010.

B. 1000.

C. 1001.

D. 1100.

Q3. List which pins need to be connected together on a 7493 to make a MOD-12 counter..

A. 12 to 1, 11 to 3, 9 to 2.

B. 12 to 1, 11 to 3, 12 to 2.

C. 12 to 1, 11 to 3, 8 to 2.

D. 12 to 1, 11 to 3, 1 to 2.

Answer= 12 to 1, 11 to 3, 8 to 2

Q4. How can a digital one-shot be implemented using HDL?.

A. By using a resistor and a capacitor.

B. By applying the concept of a counter.

C. By using a library function.

D. By applying a level trigger.

Answer= By applying the concept of a counter

Q5. Integrated-circuit counter chips are used in numerous applications including:.

A. timing operations, counting operations, seQncing, and freQncy multiplication.

B. timing operations, counting operations, seQncing, and freQncy division.

C. timing operations, decoding operations, seQncing, and freQncy multiplication.

D. data generation, counting operations, seQncing, and freQncy multiplication.

Answer= timing operations, counting operations, seQncing, and freQncy division

Q6. Synchronous construction reduces the delay time of a counter to the delay of:.

A. all flip-flops and gates.

B. all flip-flops and gates after a 3 count.

C. a single gate.

D. a single flip-flop and a gate.

Answer= a single flip-flop and a gate

Q7. Synchronous counters eliminate the delay problems encountered with asynchronous counters because the:.

A. input clock pulses are applied only to the first and last stages.

B. input clock pulses are applied only to the last stage.

C. input clock pulses are not used to activate any of the counter stages.

D. input clock pulses are applied simultaneously to each stage.

Answer= input clock pulses are applied simultaneously to each stage

Q8. What is the difference between combinational logic and seQntial logic?.

A. Combinational circuits are not triggered by timing pulses, seQntial circuits are triggered by timing pulses..

B. Combinational and seQntial circuits are both triggered by timing pulses..

C. Neither circuit is triggered by timing pulses..

D. All of the mentioned.

Answer= Combinational circuits are not triggered by timing pulses, seQntial circuits are triggered by timing pulses.

Q9. What is the difference between a 7490 and a 7492?.

A. 7490 is a MOD-12, 7492 is a MOD-10.

B. 7490 is a MOD-12, 7492 is a MOD-16.

C. 7490 is a MOD-16, 7492 is a MOD-10.

D. 7490 is a MOD-10, 7492 is a MOD-12.

Answer= 7490 is a MOD-10, 7492 is a MOD-12

Q10. When two counters are cascaded, the overall MOD number is equal to the ________ of their individual MOD numbers..

A. product.

B. sum.

C. log.

D. reciprocal.

Q11. A MOD-12 and a MOD-10 counter are cascaded. Determine the output freQncy if the input clock freQncy is 60 MHz..

A. 500 kHz.

B. 1,500 kHz.

C. 6 MHz.

D. 5 MHz.

Q12. How many AND gates would be required to completely decode ALL the states of a MOD-64 counter, and how many inputs must each AND gate have?.

A. 128 gates, 6 inputs to each gate.

B. 64 gates, 5 inputs to each gate.

C. 64 gates, 6 inputs to each gate.

D. 128 gates, 5 inputs to each gate.

Answer= 64 gates, 6 inputs to each gate

Q13. A BCD counter is a ________..

A. binary counter.

B. full-modulus counter.

D. divide-by-10 counter.

Q14. How many flip-flops are required to construct a decade counter?.

A. 10.

B. 8.

C. 5.

D. 4.

Q15. The terminal count of a typical modulus-10 binary counter is ________..

A. 000 0.

B. 1010.

C. 1001.

D. 1111.

Q16. A seven-segment, common-anode LED display is designed for:.

A. all cathodes to be wired together.

B. one common LED.

C. a HIGH to turn off each segment.

D. disorientation of segment modules.

Answer= a HIGH to turn off each segment

Q17. To operate correctly, starting a ring counter requires:.

A. clearing one flip-flop and presetting all the others..

B. clearing all the flip-flops..

C. presetting one flip-flop and clearing all the others..

D. presetting all the flip-flops..

Answer= presetting one flip-flop and clearing all the others.

Q18. Which of the following is an invalid output state for an 8421 BCD counter?.

A. 1110.

B. 000 0.

C. 00 10.

D. 000 1.

Q19. How many different states does a 3-bit asynchronous counter have?.

A. 2.

B. 4.

C. 8.

D. 16.

Q20. A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagation delay. The total propagation delay (tp(tot)) is ________..

A. 12 ms.

B. 24 ns.

C. 48 ns.

D. 60 ns.

Q21. One of the major drawbacks to the use of asynchronous counters is:.

A. low-freQncy applications are limited because of internal propagation delays.

B. high-freQncy applications are limited because of internal propagation delays.

C. asynchronous counters do not have major drawbacks and are suitable for use in high- and low-freQncy counting applications.

D. asynchronous counters do not have propagation delays and this limits their use in high-freQncy applications.

Answer= high-freQncy applications are limited because of internal propagation delays

Q22. Three cascaded modulus-5 counters have an overall modulus of ________..

A. 5.

B. 25.

C. 125.

D. 500.

Q23. An asynchronous 4-bit binary down counter changes from count 2 to count 3. How many transitional states are required?.

A. One.

B. Two.

C. Fifteen.

D. None of the mentioned.

Q24. The final output of a modulus-8 counter occurs one time for every ________..

A. 8 clock pulses.

B. 16 clock pulses.

C. 24 clock pulses.

D. 32 clock pulses.

Q25. A 4-bit up/down binary counter is in the DOWN mode and in the 1100 state. To what state does the counter go on the next clock pulse?.

A. 1101.

B. 1011.

C. 1111.

D. 000 0.

Q26. A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ________..

A. 15 ns.

B. 30 ns.

C. 45 ns.

D. 60 ns.

Q27. The terminal count of a 3-bit binary counter in the DOWN mode is ________..

A. 00 0.

B. 111.

C. 101.

D. 0 10.

Q28. The hexadecimal equivalent of 15,536 is ________..

A. 3CB0.

B. 3C66.

C. 63C0.

D. 6300.

Q29. In a VHDL retriggerable edge-triggered one-shot, which condition will not exist when a clock edge occurs?.

A. A trigger edge has occurred and we must load the counter..

B. The counter is zero and we need to keep it at zero..

C. The shift register is reset..

D. The counter is not zero and we need to count down by one..

Answer= The shift register is reset.

Q30. Synchronous (parallel) counters eliminate the delay problems encountered with asynchronous (ripple) counters because the:.

A. input clock pulses are applied only to the first and last stages..

B. input clock pulses are applied only to the last stage..

C. input clock pulses are applied simultaneously to each stage..

D. input clock pulses are not used to activate any of the counter stages..

Answer= input clock pulses are applied simultaneously to each stage.

Q31. Three cascaded decade counters will divide the input freQncy by ________..

A. 10.

B. 20.

C. 100.

D. 1,000.

Q32. A counter with a modulus of 16 acts as a ________..

A. divide-by-8 counter.

B. divide-by-16 counter.

C. divide-by-32 counter.

D. divide-by-64 counter.

Q33. What is the difference between a 7490 and a 7493?.

A. 7490 is a MOD-10, 7493 is a MOD-16.

B. 7490 is a MOD-16, 7493 is a MOD-10.

C. 7490 is a MOD-12, 7493 is a MOD-16.

D. 7490 is a MOD-10, 7493 is a MOD-12.

Answer= 7490 is a MOD-10, 7493 is a MOD-16

Q34. A ripple counter's speed is limited by the propagation delay of:.

A. each flip-flop.

B. all flip-flops and gates.

C. the flip-flops only with gates.

D. only circuit gates.

Q35. A 4-bit counter has a maximum modulus of ________..

A. 3.

B. 6.

C. 8.

D. 16.

Q36. Which of the following statements best describes the operation of a synchronous up-/down-counter?.

A. The counter can count in either direction, but must continue in that direction once started..

B. The counter can be reversed, but must be reset before counting in the other direction..

C. In general, the counter can be reversed at any point in its counting seQnce..

D. The count seQnce cannot be reversed, once it has begun, without first resetting the counter to zero..

Answer= In general, the counter can be reversed at any point in its counting seQnce.

Q37. The parallel outputs of a counter circuit represent the:.

A. parallel data word.

B. clock freQncy.

C. counter modulus.

D. clock count.

Q38. How many natural states will there be in a 4-bit ripple counter?.

A. 4.

B. 8.

C. 16.

D. 32.

Q39. List which pins need to be connected together on a 7492 to make a MOD-12 counter..

A. 1 to 12, 11 to 6, 9 to 7.

B. 1 to 12, 12 to 6, 11 to 7.

C. 1 to 12, 9 to 6, 8 to 7.

D. 1 to 12.

Q40. A principle regarding most display decoders is that when the correct input is present, the related output will switch:.

A. HIGH.

B. to high impedance.

C. to an open.

D. LOW.

Q41. A modulus-10 counter must have ________..

A. 10 flip-flops.

B. flip-flops.

C. 2 flip-flops.

D. synchronous clocking.

Q42. For a one-shot application, how can HDL code be used to make a circuit respond once to each positive transition on its trigger input?.

A. By using a counter.

B. By using an active clock.

C. By using an immediate reload.

D. By using edge trapping.

Q43. Which is not an example of a truncated modulus?.

A. 8.

B. 9.

C. 11.

D. 15.

Q44. Four cascaded modulus-10 counters have an overall modulus of ________..

A. 10.

B. 100.

C. 1,000.

D. 10,000.

Q45. What is the maximum delay that can occur if four flip-flops are connected as a ripple counter and each flip-flop has propagation delays of tPHL = 22 ns and tPLH = 15 ns?.

A. 15 ns.

B. 22 ns.

C. 60 ns.

D. 88 ns.

Q46. Which of the following statements are true?.

A. Asynchronous events do not occur at the same time..

B. Asynchronous events are controlled by a clock..

C. Synchronous events do not need a clock to control them..

D. Only asynchronous events need a control clock..

Answer= Asynchronous events do not occur at the same time.

Q47. Which of the following groups of logic devices would be the minimum required for a MOD-64 synchronous counter?.

A. Five flip-flops, three AND gates.

B. Seven flip-flops, five AND gates.

C. Four flip-flops, ten AND gates.

D. Six flip-flops, four AND gates.

Answer= Six flip-flops, four AND gates

Q48. Why can a synchronous counter operate at a higher freQncy than a ripple counter?.

A. The flip-flops change one after the other..

B. The flip-flops change at the same time..

C. A synchronous counter cannot operate at higher freQncies..

D. A ripple counter is faster..

Answer= The flip-flops change at the same time.

Q49. A multiplexed display being driven by a logic circuit:.

A. accepts data inputs from one line and passes this data to multiple output lines.

B. accepts data inputs from several lines and allows one of them at a time to pass to the output.

C. accepts data inputs from multiple lines and passes this data to multiple output lines.

D. accepts data inputs from several lines and multiplexes this input data to four BCD lines.

Answer= accepts data inputs from several lines and allows one of them at a time to pass to the output

Q50. What is meant by parallel load of a counter?.

A. Each FF is loaded with data on a separate clock..

B. The counter is cleared..

C. All FFs are preset with data..

D. None of the mentioned.

Answer= All FFs are preset with data.

Q51. Which of the following is an example of a counter with a truncated modulus?.

A. 8.

B. 13.

C. 16.

D. 32.

Q52. Which of the following is a type of shift register counter?.

B. Binary.

C. Ring.

D. BCD.

Q53. MOD-6 and MOD-12 counters and multiples are most commonly used as:.

A. freQncy counters.

B. multiplexed displays.

C. digital clocks.

D. power consumption meters.

Q54. Which of the following is an invalid state in an 8421 BCD counter?.

A. 00 11.

B. 1001.

C. 1000.

D. 1100.

Q55. After 10 clock cycles, and assuming that the DATA input had returned to 0 following the storage seQnce, what values would be stored in Q4, Q3, Q2, Q1, Q0 of the register in Figure 7-5?.

A. 0,1,0,1,1.

B. 1,1,0,1,0.

C. 1,0,1,0,1.

D. 0,0,0,0,0.

Q56. How many different states does a 2-bit asynchronous counter have?.

A. 1.

B. 2.

C. 4.

D. 8.

Q57. A 12 MHz clock freQncy is applied to a cascaded counter containing a modulus-5 counter, a modulus-8 counter, and a modulus-10 counter. The lowest output freQncy possible is ________..

A. 10 kHz.

B. 20 kHz.

C. 30 kHz.

D. 60 kHz.

Q58. The bit seQnce 0010 is serially entered (right-most bit first) into a 4-bit parallel out shift register that is initially clear. What are the Q outputs after two clock pulses?.

A. 000 0.

B. 00 10.

C. 1000.

D. 1111.

Q59. What is a shift register that will accept a parallel input, or a bidirectional serial load and internal shift features, called?.

A. tristate.

B. end around.

C. universal.

D. conversion.