# Digital Arithmetic Operation in Digital Logic Design MCQs

Q1. What is the first thing you will need if you are going to use a macrofunction?.

A. A complicated design project.

B. An experienced design engineer.

C. Good documentation.

D. Experience in HDL.

Q2. Solve this BCD problem: 0100 + 0110 =

A. 00010000(BCD).

B. 00010111(BCD).

C. 00001011(BCD).

D. 00010011(BCD).

Q3. What are constants in VHDL code?.

A. Fixed numbers represented by a name.

B. Fixed variables used in functions.

C. Fixed number types.

D. Constants do not exist in VHDL code..

Answer= Fixed numbers represented by a name

Q4. The most commonly used system for representing signed binary numbers is the:.

A. 2's-complement system..

B. 1's-complement system..

C. 10's-complement system..

D. sign-magnitude system..

B. Full adders can handle double-digit numbers..

C. Full adders have a carry input capability..

D. Half adders can handle only single-digit numbers..

Q6. The decimal value for E(16) is:.

A. 12(10).

B. 13(10).

C. 14(10).

D. 15(10).

A. determine sign and magnitude.

B. reduce propagation delay.

C. add a 1 to complemented inputs.

D. increase ripple delay.

Q8. Add the following hex numbers: 0110(16) + 10010(16).

A. 10120(16).

B. 10020(16).

C. 11120(16).

D. 120(16).

Q9. Adding in binary, a decimal 26 + 27 will produce a sum of:.

A. 111010.

B. 110110.

C. 110101.

D. 101011.

Q10. How many basic binary subtraction operations are possible?.

A. 4.

B. 3.

C. 2.

D. 1.

Q11. When performing subtraction by addition in the 2's-complement system:.

A. the minuend and the subtrahend are both changed to the 2's-complement..

B. the minuend is changed to 2's-complement and the subtrahend is left in its original form..

C. the minuend is left in its original form and the subtrahend is changed to its 2's-complement..

D. the minuend and subtrahend are both left in their original form..

Answer= the minuend is left in its original form and the subtrahend is changed to its 2's-complement.

Q12. When 1100010 is divided by 0101, what is the decimal remainder?.

A. 2.

B. 3.

C. 4.

D. 6.

Q13. What is the most important operation in binary-coded decimal (BCD) arithmetic?.

B. subtraction.

C. multiplication.

D. division.

Q14. The range of positive numbers when using an eight-bit two's-complement system is:.

A. 0 to 64.

B. 0 to 100.

C. 0 to 127.

D. 0 to 256.

Q15. What are the two types of basic adder circuits?.

A. sum and carry.

C. asynchronous and synchronous.

D. one- and two's-complement.

Q16. How many inputs must a full-adder have?.

A. 4.

B. 2.

C. 5.

D. 3.

Q17. Solve this binary problem: 01110010 - 01001000 =

A. 000 11010.

B. 00 101010.

C. 0 1110010.

D. 00 111100.

A. It is slower than the ripple-carry adder..

B. It is easier to implement logically than a full adder..

C. It is faster than a ripple-carry adder..

Q19. Perform the following hex subtraction: ACE(16)�- 999(16)�=

A. 235(16).

B. 135(16).

C. 35(16).

D. 335(16).

Q20. Which of the following is correct for full adders?.

C. Full adders are limited to two inputs since there are only two binary digits..

D. In a parallel full adder, the first stage may be a half adder..

A. The interconnections are more complex..

B. More stages are required to a full adder..

C. It is slow due to propagation time..

D. All of the above..

Answer= It is slow due to propagation time.

Q22. Solve this binary problem: 01000110 / 00001010 =

A. 0 111.

B. 10011.

C. 1001.

D. 00 11.

Q23. Convert the decimal numbers 275 and 965 to binary-coded decimal (BCD) and add. Select the BCD code groups that reflect the final answer..

A. 1101 1110 1010.

B. 1110 1010 1110.

C. 0001 0010 0100 0000.

D. 0010 0011 0100 0000.

Q24. When multiplying 13 x 11 in binary, what is the third partial product?.

A. 1011.

B. 0 0000000.

C. 100000.

D. 100001.

Q25. How many BCD adders would be required to add the numbers 973(10) + 39(10)?.

A. 3.

B. 4.

C. 5.

D. 6.

Q26. The selector inputs to an arithmetic/logic unit (ALU) determine the:.

A. selection of the IC.

B. arithmetic or logic function.

C. data word selection.

D. clock freQncy to be used.

A. two single bits and one carry bit.

B. two 2-bit binary numbers.

C. two 4-bit binary numbers.

D. two 2-bit numbers and one carry bit.

Answer= two single bits and one carry bit

Q28. The carry propagation delay in 4-bit full-adder circuits:.

A. is cumulative for each stage and limits the speed at which arithmetic operations are performed.

B. is normally not a consideration because the delays are usually in the nanosecond range.

C. decreases in direct ratio to the total number of full-adder stages.

D. increases in direct ratio to the total number of full-adder stages, but is not a factor in limiting the speed of arithmetic operations.

Answer= is cumulative for each stage and limits the speed at which arithmetic operations are performed

Q29. An input to the mode pin of an arithmetic/logic unit (ALU) determines if the function will be:.

A. one's-complemented.

B. arithmetic or logic.

C. positive or negative.

D. with or without carry.

Q30. In VHDL, what is a GENERATE statement?.

A. The start statement of a program.

B. Not used in VHDL or ADHL.

C. A way to get the computer to generate a program from a circuit diagram.

D. A way to tell the compiler to replicate several components.

Answer= A way to tell the compiler to replicate several components

Q31. Binary subtraction of a decimal 15 from 43 will utilize which two's complement?.

A. 101011.

B. 110000.

C. 0 11100.

D. 110001.

Q32. Which of the following is the primary advantage of using binary-coded decimal (BCD) instead of straight binary coding?.

A. Fewer bits are required to represent a decimal number with the BCD code..

B. BCD codes are easily converted from decimal..

C. the relative ease of converting to and from decimal.

D. BCD codes are easily converted to straight binary codes..

Answer= the relative ease of converting to and from decimal

Q33. How many inputs must a full-adder have?.

A. 2.

B. 3.

C. 4.

D. 5.

Q34. The carry propagation delay in full-adder circuits:.

A. is normally not a consideration because the delays are usually in the nanosecond range..

B. decreases in a direct ratio to the total number of FA stages..

C. is cumulative for each stage and limits the speed at which arithmetic operations are performed..

D. increases in a direct ratio to the total number of FA stages but is not a factor in limiting the speed of arithmetic operations..

Answer= is cumulative for each stage and limits the speed at which arithmetic operations are performed.

C. Half-adder does not have a carry-out..

D. Full-adder does not have a carry-out..

Q36. The summing outputs of a half- or full-adder are designated by which Greek symbol?.

A. omega.

B. theta.

C. lambda.

D. sigma.

Q37. Why is a fast-look-ahead carry circuit used in the 7483 4-bit full-adder?.

A. to decrease the cost.

B. to make it smaller.

C. to slow down the circuit.

D. to speed up the circuit.

Answer= to speed up the circuit

Q38. What logic function is the sum output of a half-adder?.

A. AND.

B. exclusive-OR.

C. exclusive-NOR.

D. NAND.

Q39. The binary adder circuit is designed to add ________ binary numbers at the same time..

A. 2.

B. 4.

C. 6.

D. 8.

Q40. How many flip-flops are required to make a MOD-32 binary counter?.

A. 3.

B. 45.

C. 5.

D. 6.