# Flip-Flops in Digital Logic Design MCQs

Q1. Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz..

A. 10.24 kHz.

B. 5 kHz.

C. 30.24 kHz.

D. 15 kHz.

Q2. Propagation delay time, t(PLH), is measured from the ________..

A. triggering edge of the clock pulse to the LOW-to-HIGH transition of the output.

B. triggering edge of the clock pulse to the HIGH-to-LOW transition of the output.

C. preset input to the LOW-to-HIGH transition of the output.

D. clear input to the HIGH-to-LOW transition of the output.

Answer= triggering edge of the clock pulse to the LOW-to-HIGH transition of the output

Q3. How many flip-flops are in the 7475 IC?.

A. 1.

B. 2.

C. 4.

D. 8.

Q4. How many flip-flops are required to produce a divide-by-128 device?.

A. 1.

B. 4.

C. 6.

D. 7.

Q5. Which is not an Altera primitive port identifier?.

A. clk.

B. ena.

C. clr.

D. prn.

Q6. The timing network that sets the output freQncy of a 555 astable circuit contains ________..

A. three external resistors are used.

B. two external resistors and an external capacitor are used.

C. an external resistor and two external capacitors are used.

D. no external resistor or capacitor is required.

Answer= two external resistors and an external capacitor are used

Q7. The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ________..

A. parity error checking.

B. ones catching.

C. digital discrimination.

D. digital filtering.

Q8. What is another name for a one-shot?.

A. Monostable.

B. Multivibrator.

C. Bistable.

D. Astable.

Q9. On a master-slave flip-flop, when is the master enabled?.

A. when the gate is LOW.

B. when the gate is HIGH.

C. both of the above.

D. neither of the above.

Answer= when the gate is HIGH

Q10. One example of the use of an S-R flip-flop is as a(n):.

A. racer.

B. astable oscillator.

C. binary storage register.

D. transition pulse generator.

Q11. What is the difference between the 7476 and the 74LS76?.

A. the 7476 is master-slave, the 74LS76 is master-slave.

B. the 7476 is edge-triggered, the 74LS76 is edge-triggered.

C. the 7476 is edge-triggered, the 74LS76 is master-slave.

D. the 7476 is master-slave, the 74LS76 is edge-triggered.

Answer= the 7476 is master-slave, the 74LS76 is edge-triggered

Q12. With regard to a D latch, ________..

A. the Q output follows the D input when EN is LOW.

B. the Q output is opposite the D input when EN is LOW.

C. the Q output follows the D input when EN is HIGH.

D. the Q output is HIGH regardless of EN's input state.

Answer= the Q output follows the D input when EN is HIGH

Q13. A J-K flip-flop is in a "no change" condition when ________..

A. J = 1, K = 1.

B. J = 1, K = 0.

C. J = 0, K = 1.

D. J = 0, K = 0.

Answer= J = 0, K = 0

Q14. A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the:.

A. clock is LOW.

B. slave is transferring.

C. flip-flop is reset.

D. clock is HIGH.

Q15. Which of the following describes the operation of a positive edge-triggered D flip-flop?.

A. If both inputs are HIGH, the output will toggle..

B. The output will follow the input on the leading edge of the clock..

C. When both inputs are LOW, an invalid state exists..

D. The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock..

Q16. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________..

A. constantly LOW.

B. constantly HIGH.

C. a 20 kHz square wave.

D. a 10 kHz square wave.

Answer= a 10 kHz square wave

Q17. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________..

A. the clock pulse is LOW.

B. the clock pulse is HIGH.

C. the clock pulse transitions from LOW to HIGH.

D. the clock pulse transitions from HIGH to LOW.

Answer= the clock pulse transitions from LOW to HIGH

Q18. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________..

A. SET.

B. RESET.

C. clear.

D. invalid.

Q19. In VHDL, how many inputs will a primitive JK flip-flop have?.

A. 2.

B. 3.

C. 4.

D. 5.

Q20. Does the cross-coupled NOR flip-flop have active-HIGH or active-LOW set and reset inputs?.

A. active-HIGH.

B. active-LOW.

C. Both of the mentioned.

D. None.

Q21. The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the:.

A. edge-detection circuit..

B. NOR latch..

C. NAND latch..

D. pulse-steering circuit..

Q22. Which of the following is not generally associated with flip-flops?.

A. Hold time.

B. Propagation delay time.

C. Interval time.

D. Set up time.

Q23. Edge-triggered flip-flops must have:.

A. very fast response times.

B. at least two inputs to handle rising and falling edges.

C. positive edge-detection circuits.

D. negative edge-detection circuits.

Q24. What is one disadvantage of an S-R flip-flop?.

A. It has no enable input..

B. It has an invalid state..

C. It has no clock input..

D. It has only a single output..

Answer= It has an invalid state.

Q25. To completely load and then unload an 8-bit register requires how many clock pulses?.

A. 2.

B. 4.

C. 8.

D. 16.

Q26. What is one disadvantage of an�S-R�flip-flop?.

A. It has no enable input..

B. It has an invalid state..

C. It has no clock input..

D. It has only a single output..

Answer= It has an invalid state.

Q27. Which of the following best describes the action of pulse-triggered FF's?.

A. The clock and the S-R inputs must be pulse shaped..

B. The data is entered on the leading edge of the clock, and transferred out on the trailing edge of the clock..

C. A pulse on the clock transfers data from input to output..

D. The synchronous inputs must be pulsed..

Answer= The data is entered on the leading edge of the clock, and transferred out on the trailing edge of the clock.

Q28. An invalid condition in the operation of an active-HIGH input S-R latch occurs when ________..

A. HIGHs are applied simultaneously to both inputs S and R.

B. LOWs are applied simultaneously to both inputs S and R.

C. a LOW is applied to the S input while a HIGH is applied to the R input.

D. a HIGH is applied to the S input while a LOW is applied to the R input.

Answer= HIGHs are applied simultaneously to both inputs S and R

Q29. Edge-triggered flip-flops must have:.

A. very fast response times..

B. at least two inputs to handle rising and falling edges..

C. a pulse transition detector..

D. active-LOW inputs and complemented outputs..

Q30. As a general rule for stable flip-flop triggering, the clock pulse rise and fall times must be:.

A. very long..

B. very short..

C. at a maximum value to enable the input control signals to stabilize..

D. of no conseQnce as long as the levels are within the determinate range of value..

Q31. A positive edge-triggered D flip-flop will store a 1 when ________..

A. the D input is HIGH and the clock transitions from HIGH to LOW.

B. the D input is HIGH and the clock transitions from LOW to HIGH.

C. the D input is HIGH and the clock is LOW.

D. the D input is HIGH and the clock is HIGH.

Answer= the D input is HIGH and the clock transitions from LOW to HIGH

Q32. If an input is activated by a signal transition, it is ________..

A. edge-triggered.

B. toggle triggered.

C. clock triggered.

D. noise triggered.

Q33. Which is not a real advantage of HDL?.

A. Using higher levels of abstraction.

B. Tailoring components to exactly fit the needs of the project.

C. The use of graphical tools.

D. Using higher levels of abstraction and tailoring components to exactly fit the needs of the project.

Answer= The use of graphical tools

Q34. Two J-K flip-flops with their J-K inputs tied HIGH are cascaded to be used as counters. After four input clock pulses, the binary count is ________..

A. 0 0.

B. 11.

C. 0 1.

D. 10.

Q35. Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?.

A. cross coupling.

B. gate impedance.

C. low input voltages.

D. asynchronous operation.

Q36. In VHDL, how is each instance of a component addressed?.

A. A name followed by a colon and the name of the library primitive.

B. A name followed by a semicolon and the component type.

C. A name followed by the library being used.

D. A name followed by the component library number.

Answer= A name followed by a colon and the name of the library primitive

Q37. The output of a gated S-R�flip-flop changes only if the:.

A. flip-flop is set.

B. control input data has changed.

C. flip-flop is reset.

D. input data has no change.

Answer= control input data has changed

Q38. In VHDL, in which declaration section is a COMPONENT declared?.

A. Architecture.

B. Library.

C. Entity.

D. Port map.

Q39. If both inputs of an S-R flip-flop are low, what will happen when the clock goes HIGH?.

A. An invalid state will exist..

B. No change will occur in the output..

C. The output will toggle..

D. The output will reset..

Answer= No change will occur in the output.

Q40. A push-button switch is used to input data to a register. The output of the register is erratic. What could be causing the problem?.

A. The power supply is probably noisy..

B. The switch contacts are bouncing..

C. The socket contacts on the register IC are corroded..

D. The register IC is intermittent and failure is imminent..

Answer= The switch contacts are bouncing.

Q41. The pulse width of a one-shot circuit is determined by ________..

A. a resistor and capacitor.

B. two resistors.

C. two capacitors.

D. none of the above.

Q42. If both inputs of an�S-R�flip-flop are LOW, what will happen when the clock goes high?.

A. No change will occur in the output..

B. An invalid state will exist..

C. The output will toggle..

D. The output will reset..

Answer= No change will occur in the output.

Q43. Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input freQncy (fin) to the first flip-flop is 32 kHz, the output freQncy (fout) is ________..

A. 1 kHz.

B. 2 kHz.

C. 4 kHz.

D. 16 kHz.